Satwik Patnaik, Mohammed Ashraf, Johann Knechtel, and Ozgur Sinanoglu
Layout camouflaging (LC) is a promising technique to protect chip design intellectual property (IP) from reverse engineers. Most prior art, however, cannot leverage the full potential of LC due to excessive overheads and/or their limited scope on an FEOL-centric and accordingly customized manufacturing process. If at all, most existing techniques can be reasonably applied only to selected parts of a chip— we argue that such “small-scale or custom camouflaging” will eventually be circumvented, irrespective of the underlying technique.